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VRD312 数据表(PDF) 39 Page - Microchip Technology |
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VRD312 数据表(HTML) 39 Page - Microchip Technology |
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39 / 416 page ![]() 2016-2018 Microchip Technology Inc. DS30010118D-page 39 PIC24FJ256GA705 FAMILY REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0 — — — —IPL3(1) PSV(2) — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility (PSV) in Data Space Enable(2) 1 = Program space is visible in Data Space 0 = Program space is not visible in Data Space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level; see Register 3-1 for bit description. 2: If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of reading from the PSV section of program memory. This bit is not individually addressable. |
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