VRD312 datasheet(66/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 66

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5.1.6

CHANNEL PRIORITY

Each DMA channel functions independently of the

others, but also competes with the others for access to

the data and DMA buses. When access collisions

occur, the DMA Controller arbitrates between the

channels using a user-selectable priority scheme. Two

schemes are available:

• Round-Robin: When two or more channels

collide, the lower numbered channel receives

priority on the first collision. On subsequent colli-

sions, the higher numbered channels each

receive priority, based on their channel number.

• Fixed: When two or more channels collide, the

lowest numbered channel always receives

priority, regardless of past history; however, any

channel being actively processed is not available

for an immediate retrigger. If a higher priority

channel is continually requesting service, it will be

scheduled for service after the next lower priority

channel with a pending request.

5.2

Typical Setup

To set up a DMA channel for a basic data transfer:

Enable the DMA Controller (DMAEN = 1) and

select an appropriate channel priority scheme

by setting or clearing PRSSEL.

Program DMAH and DMAL with the appropriate

upper and lower address boundaries for data

RAM operations.

Select the DMA channel to be used and disable

its operation (CHEN = 0).

Program the appropriate source and destination

addresses for the transaction into the channel’s

DMASRCn and DMADSTn registers. For PIA

mode addressing, use the base address value.

Program the DMACNTn register for the number

of triggers per transfer (One-Shot or Continuous

modes) or the number of words (bytes) to be

transferred (Repeated modes).

Set or clear the SIZE bit to select the data size.

Program the TRMODE<1:0> bits to select the

Data Transfer mode.

Program the SAMODE<1:0> and DAMODE<1:0>

bits to select the addressing mode.

Enable the DMA channel by setting CHEN.

10. Enable the trigger source interrupt.

5.3

Peripheral Module Disable

Unlike other peripheral modules, the channels of the

DMA Controller cannot be individually powered down

using the Peripheral Module Disable (PMD) registers.

Instead, the channels are controlled as two groups. The

DMA0MD bit (PMD7<4>) selectively controls DMACH0

through DMACH3. The DMA1MD bit (PMD7<5>)

controls DMACH4 and DMACH5. Setting both bits

effectively disables the DMA Controller.

5.4

DMA Registers

The DMA Controller uses a number of registers to con-

trol its operation. The number of registers depends on

the number of channels implemented for a particular

device.

There are always four module-level registers (one

control and three buffer/address):

• DMACON: DMA Engine Control Register

(Register 5-1)

• DMAH and DMAL: DMA High and Low Address

Limit Registers

• DMABUF: DMA Data Buffer

Each of the DMA channels implements five registers

(two control and three buffer/address):

• DMACHn: DMA Channel n Control Register

(Register 5-2)

• DMAINTn: DMA Channel n Interrupt Register

(Register 5-3)

• DMASRCn: DMA Data Source Address Pointer

for Channel n

• DMADSTn: DMA Data Destination Address Pointer

for Channel n

• DMACNTn: DMA Transaction Counter for

Channel n

For PIC24FJ256GA705 family devices, there are a

total of 34 registers.

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