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MPFS250TLS 数据表(PDF) 127 Page - Microchip Technology |
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MPFS250TLS 数据表(HTML) 127 Page - Microchip Technology |
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127 / 128 page  Table 166 • NRBG CAL Delay In CPU Clock-Cycles Athena TeraFire Crypto Core Clock-Cycles Message Size (Bits) Modes 3076 18221 Instantiate: strength, s=256, 3 84-bit nonce, 384-bit personal- ization string 1056 13585 Reseed: no additional input, s=256 995 15922 Reseed: 384-bit additional in- put, s=256 1672 15262 128 Generate: (no additional in- put), prediction resistance en- abled, s=256 7837 27169 8K 781 2138 128 Generate: (no additional in- put), prediction resistance dis- abled, s=256 7837 14045 8K 1620 21299 128 Generate: (384-bit additional input), prediction resistance enabled, s=256 8563 33206 8K 1507 11657 128 Generate: (384-bit additional input), prediction resistance disabled, s=256 8563 23564 8K 502 761 Un-instantiate 123 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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