CC2400-RTR1 datasheet(68/84 Pages) TI

68 / 84 page

CC2400

SWRS042A

Page 68 of 83

Bit

Field Name

Reset

R/W

Description

9:8

AFC_SETTLING[1:0]

R/W

Controls how many max-min pairs that are used to compute the

output.

00: 1 pair

01: 2 pairs

10: 4 pairs

11: 8 pairs

7:0

AFC_DELTA[7:0]

R/W

Programmable level used in AFC-algorithm that indicates the

expected frequency deviation of the received signal. See page

42 for further details.

MDMTST1 (0x15) - Modem Test Register 1

Bit

Field Name

Reset

R/W

Description

15:7

Reserved, write as 0.

6:0

BSYNC_THRESHOLD[6:0]

R/W

Threshold value used in clock recovery algorithm. Sets the level

for when re-synchronization takes place.

DACTST (0x16) - DAC Test Register

Bit

Field Name

Reset

R/W

Description

Reserved, write as 0.

14:12

DAC_SRC[2:0]

R/W

The TX DACs data source is selected by DAC_SRC according

to:

0: Normal operation (from modulator).

1: The DAC_I_O and DAC_Q_O override values below.

2: From ADC

3: I/Q after digital down-mixing and channel filtering.

4: Full-spectrum White Noise (from PRNG.)

5: RX signal magnitude / frequency filtered (from demodulator).

6: RSSI / RX frequency offset estimation.

7: HSSD module.

This feature will often require the DACs to be manually turned on

in MANOVR and PAMTST.ATESTMOD_MODE=4.

11:6

DAC_I_O[5:0]

R/W

I-branch DAC override value.

5:0

DAC_Q_O[5:0]

R/W

Q-branch DAC override value.

CC2400-RTR1 数据表(PDF) 68 Page - Texas Instruments

CC2400-RTR1 数据表(HTML) 68 Page - Texas Instruments

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CC2400-RTR1 数据表(PDF) 68 Page - Texas Instruments

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