数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CC2400-RTR1 数据表(PDF) 12 Page - Texas Instruments

Click here to check the latest version.
部件名 CC2400-RTR1
功能描述  2.4 GHz Low-Power RF Transceiver
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CC2400-RTR1 数据表(HTML) 12 Page - Texas Instruments

Back Button CC2400-RTR1 Datasheet HTML 8Page - Texas Instruments CC2400-RTR1 Datasheet HTML 9Page - Texas Instruments CC2400-RTR1 Datasheet HTML 10Page - Texas Instruments CC2400-RTR1 Datasheet HTML 11Page - Texas Instruments CC2400-RTR1 Datasheet HTML 12Page - Texas Instruments CC2400-RTR1 Datasheet HTML 13Page - Texas Instruments CC2400-RTR1 Datasheet HTML 14Page - Texas Instruments CC2400-RTR1 Datasheet HTML 15Page - Texas Instruments CC2400-RTR1 Datasheet HTML 16Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 84 page
background image
CC2400
SWRS042A
Page 12 of 83
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
PLL lock time (RX / TX turn-on
time)
40
µs
Until within ± 10 kHz
Step size is 1MHz, no calibration.
Note: Calibration should be
performed for frequency changes
> 8 MHz.
PLL turn-on time from IDLE mode,
crystal oscillator on
100
µs
Crystal oscillator running.
Calibration time included.
Table 8 Frequency synthesizer characteristics
13 Digital Inputs/Outputs
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Signal levels are referred to the
voltage level at the pin DVDD3.3.
Logic "0" input voltage
0
0.3*
DVDD
V
Logic "1" input voltage
0.7*
DVDD
DVDD
V
Logic "0" output voltage
0
0.4
V
Output current −8 mA,
3.3 V supply voltage
Logic "1" output voltage
2.5
DVDD
V
Output current 8 mA,
3.3 V supply voltage
Logic "0" input current
NA
−1
µA
Input signal equals GND
Logic "1" input current
NA
1
µA
Input signal equals DVDD
DIO setup time
20
ns
TX un-buffered mode, minimum
time DIO must be ready before
the positive edge of DCLK
DIO hold time
10
ns
TX un-buffered mode, minimum
time DIO must be held after the
positive edge of DCLK
Serial interface (SCLK, SI, SO and
CSn) timing specification
See Table 12 page 22
Table 9 Digital input/output characteristics



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com