9.8

CTRL_REG3 (12h)

Control register 3 (R/W)

7

6

5

4

3

2

1

0

0

0

0

0

INT_H_L

0

PP_OD

IF_ADD_INC

INT_H_L

Select interrupt active-high, active-low. Default value: 0

(0: active-high; 1: active-low)

PP_OD

Push-pull/open-drain selection on interrupt pin. Default value: 0

(0: push-pull; 1: open-drain)

IF_ADD_INC

Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1

(0: disable, 1: enable)

The INT_H_L bit selects an interrupt active-high/low value.

The PP_OD bit selects push-pull/open-drain on the interrupt pin.

The IF_ADD_INC bit enables the address to be automatically incremented during a multiple byte access with a

serial interface (SPI or I²C).

9.9

CTRL_REG4 (13h)

Control register 4 (R/W)

7

6

5

4

3

2

1

0

0

DRDY_PLS

DRDY

INT_EN

-

INT_F_FULL

INT_F_WTM

INT_F_OVR

DRDY_PLS(1)

Data_Ready pulsed on INT pin. Default value: 0

(0: disable; 1: enable data-ready pulsed on INT pin, pulse width around 5 μs)

DRDY

Date-Ready signal on INT pin. Default value: 0

(0: disable; 1: enable)

INT_EN

Interrupt signal on INT pin. Default value: 0

(0: disable; 1: enable)

INT_F_FULL

FIFO full flag on INT pin. Default value: 0

(0: FIFO empty; 1: FIFO full with 128 unread samples)

INT_F_WTM

FIFO threshold (watermark) status on INT pin. Default value: 0

(0: FIFO is lower than WTM level; 1: FIFO is equal to or higher than WTM level)

INT_F_OVR

FIFO overrun status on INT pin. Default value: 0

(0: not overwritten; 1: at least one sample in the FIFO has been overwritten)

1. This bit is used together with the DRDY bit and it can be ignored if DRDY = 0.

LPS22DF

CTRL_REG3 (12h)

DS13316 - Rev 1

page 37/54