OPA310 datasheet(35/55 Pages) TI

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power connections of the board and propagate to the

power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a

low-impedance path to ground.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. One bypass capacitor from V+ to ground is adequate for single-supply

applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care

to physically separate digital and analog grounds, paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.

If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as

opposed to running the traces in parallel with the noisy trace.

• Place the external components as close to the device as possible, as shown in Layout Example. Keeping R1

and R2 close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive

part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• TI recommends cleaning the PCB following board assembly for best performance.

• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly

to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,

post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

–

V+

INPUT

V-

OUTPUT

Figure 11-1. Schematic for Noninverting Configuration Layout Example

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OPA310, OPA2310, OPA4310

SBOSAA1C – APRIL 2022 – REVISED SEPTEMBER 2022

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