7.7 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VSHDN_IL

Logic low

threshold

voltage

(amplifier

disabled)

(V–) + 0.2

V

tON

Amplifier enable

time (full

shutdown) (7) (1)

G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–

0.9

1.3

µs

tOFF

Amplifier disable

time (7)

G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V–

1

µs

IB_SHDN

SHDN pin input

bias current (per

pin)

(V+) ≥ SHDN ≥ (V–) + 1 V

50

nA

(V–) ≤ SHDN ≤ (V–) + 0.2 V

100

(1)

Max data is specified based on characterization results.

(2)

Min data is specified based on characterization results.

(3)

Typical input current noise data is specified based on design simulation results.

(4)

Third-order filter; bandwidth = 80 kHz at –3 dB.

(5)

Short circuit current specified here is the average of sourcing and sinking short circuit currents.

(6)

AOL is measured as the difference between (VOSA – VOSB) / (VOUTA – VOUTB). VOSA is the offset measured when the OUT pin is biased

at (V+) - 0.25 V while the device sources 50 mA and VOSB is the offset measured when the OUT pin is biased at (V–) + 0.25 V while

the device sinks 50 mA.

(7)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

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SBOSAA1C – APRIL 2022 – REVISED SEPTEMBER 2022

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