L9960T datasheet(27/95 Pages) STMICROELECTRONICS

27 / 95 page

DS11115 Rev 10

27/95

L9960, L9960T

Functional description

4.1.5

Device supply electrical characteristics

Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified.

All voltages refer to GND. Currents are positive into and negative out of the specified pin.

4.2

Power on reset (POR) and SW reset

POR is a low active internal reset signal, leading the H-bridge in tri-state. It is released in

case the VDD5 is higher than the POR threshold (hysteresis implemented). The POR

input has a hysteresis to avoid unstable behaviors during ramp up and down of VDD5.

The POR is active for VDD5 from 0V to [Vpor + Vpor_hys] (POR threshold + hysteresis).

When RESET state is active, the bridge is switched to tri-state.

When VDD5 voltage increases above the POR (Power On Reset) threshold (hysteresis

implemented), the L9960 starts with all the settings reset to their default values.

In Figure 11 is shown an example of POR timing diagram.

At point 1, due to a POR condition on VDD5 supply, the POR signal is set to low and it is

released after 300 µs. L9960 is in disable state and the LBIST+HWSC (condition 2) is

Table 23. Device supply electrical characteristic

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Ips

Power supply current

VDD5 < 0.7 V; Vps < 16 V

Tj < 85 °C; L9960

-10

µA

VDD5 < 0.7 V; Vps

 16 V

Tj > 85 °C; L9960

180

µA

FPWM = 0; Iout = 0

(L9960, L9960T)

For FPWM=20 kHz; Iout = 0

(L9960)

For FPWM = 20 kHz; Iout = 0

(L9960T)

Iout

Leakage current on output

Bridge in tri-state

All current sources switched OFF

Measured between OUT1 and

OUT2

-100

100

µA

Icc

Logic-supply current

VDD5 >VDD5_uv_on

FPWM = 0, for L9960

for L9960T

FPWM = 20 kHz

for L9960

for L9960T

IVDDIO

SPI controller current

consumption on VDDIO

SDO not connected (L9960)

for L9960T

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