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L9960T 数据表(PDF) 38 Page - STMicroelectronics

部件名 L9960T
功能描述  Automotive Single/Dual H-Bridge, SPI programmable DC Brushed Motor Driver
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L9960T 数据表(HTML) 38 Page - STMicroelectronics

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Functional description
L9960, L9960T
38/95
DS11115 Rev 10
Note:
A minimum pulse width of 1 µs has to be guaranteed on driving control pins PWM/DIR for
the relative command acknlowdgement by internal logic.
In VVL mode, the bridge is controlled by these two inputs and according to the VVL status
as described in the table below:
A specific dead-time “TSW“ is implemented between high-side and low-side transistors
switching to avoid cross-conduction. It applies when switching from on-state to freewheeling
state and viceversa, regardless of the actual way to drive the H-bridge (PWD/DIR or
IN1/IN2). The total delay may be related to the switching Current slew rate selected by SPI.
The dead time is managed in the digital design, using analog feedback information from the
gate driver.
In order to avoid h-bridge misbehavior, it is strongly recommended to avoid working with
default settings: TSW_low_current = 0 is the only configuration allowed for all the
applications.
POR, BIST/HWSC and SW reset commands overwrite the configuration
TSW_low_current=0, so the application SW shall take care of resuming
TSW_low_current=1.
The bit TSW_low_current_echo is available for reading on the Configuration Request 1
register, for eventual runtime configuration check
Note:
(-) available in the D2 bit position in SPI command frame 3.
1
0
01
10
Reverse
1
1
1
0
1
0
HS Freewheeling(1)
1. It is advised against using this recirculation option in IN1/IN2 mode as L9960 is not safely protected against
external failures (i.e SCG). For IN1/IN2 mode only it is advised to recirculate (active freewheeling) on
low-side drivers only.
Table 41. IN1/IN2 mode H-bridge input (continued)
Inputs
Outputs (MOS Driver)
Condition
IN2 (DIR)
IN1 (PWM) OUT1_HS
OUT1_LS
OUT2_HS
OUT2_LS
Table 42. VVL mode H-bridge input
DIR
PWM
VVL phase
OUT1_HS
OUT1_LS
OUT2_HS
OUT2_LS
Condition
11
no active
with PWM=1
10
0
1
Forward
0
1
0
1
1
0
Reverse
x
0
T < TVVL
0
1
0
1
Freewheeling
x
0
T > TVVL
0
0
0
0
Tri-state
Table 43. TSW_low_current
Bit config
Description
Condition
0
Tsw activated on i_gate_fb only
-
1
Tsw activated on the last event between i_gate_fb or i_out_on
Reset value



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