STA8090FG datasheet(20/41 Pages) STMICROELECTRONICS

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General description

STA8090FG

20/41

DS10719 Rev 6

3.4

APB peripherals

3.4.1

CAN

The 2 CAN(a) cores perform communication according to the CAN protocol version 2.0 part

A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the

physical layer, additional transceiver hardware is required.

CAN consists of the CAN core, message RAM, message handler, control registers and

module. For communication on a CAN network, individual message objects are configured.

The message objects and identifier masks for acceptance filtering of received messages are

stored in the message RAM. All functions concerning the handling of messages are

implemented in the message handler. These functions include acceptance filtering, the

transfer of messages between the CAN core and the message RAM, and the handling of

transmission requests as well as the generation of the module interrupt.

The register set of the CAN can be accessed directly by the CPU through the module

interface. These registers are used to control/configure the CAN core and the message

handler and to access the message RAM.

CAN features



Supports CAN protocol version 2.0 part A and B



32 messages objects



Each message object has its own identifier mask



Maskable interrupt



Disabled automatic re-transmission mode for time triggered CAN applications



Programmable loop-back mode for self-test operation



Two 16-bit module interfaces to the AMBA APB bus from ARM

3.4.2

SSP

The SSP is a master interface for synchronous serial communication with peripheral

devices that have Motorola SPI.

The SSP performs serial-to-parallel conversion on data received from a peripheral device

on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on

SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories

allowing up to 32 x 32-bit values to be stored independently in both transmit and receive

modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one

to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO.

The SSP includes a programmable bit rate clock divider and prescaler to generate the serial

output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is

asserted from several internal maskable events.

a. STA8090FGB and STA8090FGBD only (see Figure 5: Ordering information scheme).

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