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STA8090FG 数据表(PDF) 34 Page - STMicroelectronics |
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STA8090FG 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 41 page ![]() Electrical characteristics STA8090FG 34/41 DS10719 Rev 6 Figure 3. SARADC connections REFP REFN AIN0 AIN1 AIN7 VREF D[9:0] SARADC ADC WRAPPER VINL1 VDD12_MVR APB Bridge2 ADC_IN1 ADC_IN2 ADC_IN8 GND Table 29. SARADC specifications Symbol Parameter Min. Typ. Max. Unit VADCIN ADC_IN input range VGND-0.3 — VINL1+0.3 V VADCCR Conversion range VGND —VREF V VREF Voltage reference 1.35 1.4 1.45 V CIN Input capacitance(1) 1. Not tested in production. 5.5 7.0 8.5 pF RIN Input mux resistance (total equivalent sampling resistance)(2) 2. Pad input capacitance included. 1.5 2.0 2.5 k FCLK Clock frequency 2.5 15 MHz CLK Clock duty cycle 45 50 55 % TSUP Start up time(1)(3) 3. From EN=1. — — 20 µs TC Conversion time — 14 cycles TS Sampling time — 3 cycles INL Performance < +/- 2 LSB DNL < +/- 2 LSB |
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