FDA803D datasheet(44/78 Pages) STMICROELECTRONICS

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Diagnostic

FDA803D

44/78

DocID031487 Rev 2

Moreover, if the high-pass filter function is enabled through IB3[2], the input offset is

eliminated, guaranteeing a complete robustness in case of any malfunction coming from the

audio signal source.

11.6

Output voltage offset detector

Output voltage offset detector aim is to detect a voltage offset on the output.

For this purpose, an internal circuit detects when the voltage value on FBP pin or on FBM

pin exceeds 1V difference with respect to Vcc/2 value, generating a fault condition. If the

fault condition persists for 90ms consecutively, the circuits sets the flag on I2C bit DB0[3]. As

soon as the fault condition is removed, both the flag DB0[3] and the 90ms counter are reset.

The implemented logic avoids false detections in case of very low signal frequency.

The feature operation is showed in Figure 55:

Figure 55. Output voltage offset detector operation

When enabled, the feature is active both in MUTE and in PLAY states.

Please note that the Output Voltage Offset Detector must not be enabled when FBP and

FBM pins are shorted with OUTP and OUTM pins, i.e. for feedback before filter

configuration: the full-swing PWM outputs don't allow the fault condition persisting for more

than 90ms even in case of offset. A valid and robust alternative is provided by the Output

Current Offset Detector.

The offset detector output is provided in two forms:



Enables the pull down on CDDiag pin, if IB4[7]='1'



Sets the flag DB0[3]='1'

FDA803D 数据表(PDF) 44 Page - STMicroelectronics