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FDA803D 数据表(PDF) 55 Page - STMicroelectronics |
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FDA803D 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 78 page  DocID031487 Rev 2 55/78 FDA803D I2S bus interface 77 13.5 Timing requirements Figure 67. I2S Interface timings Figure 68. I2S clock transition timings Table 10. I2S Interface timings Symbol Parameter Note Min Max Unit TSCK I2S clock period 40.69 ns I2S clock period tolerance 0.9 x TSCK 1.1 x TSCK I2S clock duty cycle 40 60 % TSCKH I2S clock high time 15 ns TSCKL I2S clock low time 15 ns TSCKT I2S clock transition time 6 ns TDS I2S data (and word select) setup time (before I2S clock rising edge) 8ns TDH I2S data (and word select) hold time (after I2S clock rising edge) 8ns TWSH I2S word select high time I2S standard 32 x TSCK TDM4 format 1 x TSCK 127 x TSCK TDM8 format 1 x TSCK 255 x TSCK TDM16 format 1 x TSCK 511 x TSCK |
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