DS12748 Rev 2

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HVLED001B

Application information

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7.2.4

Primary side regulation feature

The ZCD pin is also used as input of the PSR error amplifier (E/A). The reference voltage of

this loop is internally fixed to VREF,PSR and applied to the non-inverting input of the E/A.

The output of such error amplifier is connected to the FB pin where the relevant

compensation network has to be connected.

In a flyback or buck-boost topology the output voltage can be read from primary side using

an auxiliary winding of the power magnetic: in this case the output voltage is obtained using

the following equation:

Equation 2

The internal small signal model of the PSR E/A is obtained by considering the voltage gain

Figure 23:

Figure 23. PSR E/A small signal model

7.2.5

Burst mode operation

As soon as either the FB pin or OPTO pin drops below, respectively, Vbm or VOPTO,dis the

burst mode operating mode is entered. On this occurrence, the switching activity is

temporarily interrupted. If the PSR loop is controlling the application, the output voltage

value is refreshed every Trep by means of the generation of four switching pulses.

On the other hand, if the optocoupler is controlling the loop, the IC remains disabled until the

OPTO pin is above VOPTO,dis and the FB pin is above Vbm.

During IC inactivity, VCC consumption is minimized.

VREF PSR



---------------1 Rzcd

Rfb

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+







=