PTH12010LAH datasheet(21/27 Pages) TI

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DEMONSTRATION CIRCUIT

VI (5 V/div)

t − Time − 5 ms/div

Startup

Period

UVLO Threshold

VO (1 V/div)

t − Time − 10 ms/div

VO1 (1 V/div)

VO2 (1 V/div)

IO2 (5 V/div)

PTH12010W, PTH12010L

SLTS205E–JUNE 2003–REVISED APRIL 2006

Figure 21 shows the startup waveforms for the demonstration circuit shown in Figure 22. The initial rise in VO2is

the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the

output current from the PTH12010L module (IO2) is negligible until its output voltage rises above the applied

prebias.

Figure 20. PTH12020W Startup

Figure 21. Prebias Startup Waveforms

NOTES

1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now been

incorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with

a production lot date code of 0423 or later.

2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by the

voltage applied to the Track control pin, the output sinks current during the period that the track control

voltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track be

disabled when not being used. This is accomplished by connecting the Track pin to the input voltage, VI.

This raises the Track pin voltage well above the set-point voltage prior to the module’s start up, thereby

defeating the Auto-Track feature.

3. To further ensure that the regulator’s output does not sink current when power is first applied (even with a

ground signal applied to the Inhibit control pin), the input voltage must always be greater than the applied

pre-bias source. This condition must exist throughout the power-up sequence of the power system.

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