PTH12010LAH datasheet(3/27 Pages) TI

3 / 27 page

www.ti.com

ELECTRICAL CHARACTERISTICS

PTH12010W, PTH12010L

SLTS205E–JUNE 2003–REVISED APRIL 2006

TA =25°C, Vi =12V,VO = 3.3 V, Ci = 560 µF, CO =0 µF, and IO =IO max (Unless otherwise stated)

PTH12010W

CHARACTERISTICS

CONDITIONS

MIN

TYP

MAX

UNIT

60 °C, 200 LFM airflow

12(3)

Output current

1.2 V ≤ Vo≤ 5.5 V

25 °C, natural convection

12(1)

Input voltage range

Over Io range

10.8

13.2

Vo tol

Set-point voltage tolerance

±2(4)

%Vo

Regtemp Temperature variation

–40 °C < TA <85 °C±0.5

%Vo

Regline Line regulation

Over VI range

±10

Regload Load regulation

Over Io range

±12

Regtot

Total output variation

Includes set-point, line, load,

±3(2)

%Vo

–40 °C ≤ TA ≤ 85 °C

Vadj

Output voltage adjust range

Over VI range

1.2

5.5

RSET = 280 Ω,Vo =5V

RSET =2.0 kΩ,Vo =3.3 V

RSET =4.32kΩ,Vo =2.5 V

Efficiency

IO =8A

RSET = 11.5 kΩ,Vo =1.8 V

RSET = 24.3 kΩ,Vo =1.5 V

RSET = OPEN, Vo =1.2 V

Vo ≤ 2.5 V

mVpp

VO ripple (peak-to-peak)

20-MHz bandwidth

Vo ≤ 2.5 V

% VO

Io trip

Overcurrent threshold

Reset, followed by auto-recovery

1 A/µs load step, 50 to 100 % Iomax,

CO = 330 µF

Transient response

ttr

Recovery Time

µSec

Vtr

Vo over/undershoot

100

Vo adj

Margin up/down adjust

±5

IIL

–8(5)

µA

Margin input current (pins 9 /10)

Pin to GND

margin

IIL track

Track input current (pin 8)

Pin to GND

–0.13(6)

dVtrack/dt Track slew rate capability

CO≤ CO(max)

V/ms

Vi increasing

9.5

10.4

UVLO

Undervoltage lockout

Vi decreasing

8.8

Inhibit control (pin3)

VIH

Input high voltage

Referenced to GND

VI– 0.5

Open(4)

VIL

Input low voltage

–0.2

0.5

IIL inhibit Input low current

Pin to GND

0.24

Iin inh

Input standby current

Inhibit (pin 3) to GND, Track (pin 8) open

Switching frequency

Over Vi and Io ranges

300

350

400

kHz

External input capacitance

560(7)

µF

(3) See SOA curves or consult factory for appropriate derating.

(4) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a

tolerance of 1%, with 100 ppm/°C (or better) temperature stability.

(5) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.

(6) This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 8). If it is left open-circuit the module operates when input

power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do

not place an external pull-up on this pin. For further information, see the related application section.

(7) A 560 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple

current.

Submit Documentation Feedback

PTH12010LAH 数据表(PDF) 3 Page - Texas Instruments

PTH12010LAH 数据表(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

数据表下载

链接网址

PTH12010LAH 数据表(PDF) 3 Page - Texas Instruments

PTH12010LAH 数据表(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

数据表 下载

链接网址

数据表下载