7

ICS950813

Advance Information

0708—10/10/02

Pin #

Name

0

1

PWD

Bit 7

38

48MHz_DOT

Output control

RW

Disable

Enable

1

Bit 6

39

48MHz_USB/FS2**

Output control

RW

Disable

Enable

1

Bit 5

7

*ASEL/PCICLK_F2 (see note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 4

6

PCICLK_F1 (see note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 3

5

PCICLK_F0 (see note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 2

7

*ASEL/PCICLK_F2

Output control

RW

Disable

Enable

1

Bit 1

6

PCICLK_F1

Output control

RW

Disable

Enable

1

Bit 0

5

PCICLK_F0

Output control

RW

Disable

Enable

1

Note:

Pin #

Name

0

1

PWD

Bit 7

35

FS3

Frequency Selection

RW

-

-

X

Bit 6

33

FS4

Frequency Selection

RW

-

-

X

Bit 5

33

3V66_0/FS4**

Output control

RW

Disable

Enable

1

Bit 4

35

3V66_1/VCH_CLK/FS3**

Output control

RW

Disable

Enable

1

Bit 3

24

3V66_5

Output control

RW

Disable

Enable

1

Bit 2

23

3V66_4

Output control

RW

Disable

Enable

1

Bit 1

22

3V66_3

Output control

RW

Disable

Enable

1

Bit 0

21

3V66_2

Output control

RW

Disable

Enable

1

Pin #

Name

0

1

PWD

Bit 7

X

PD Mode Iref Mirror Enable

Allow Iref Mirror to be ON during

Power Down Mode

RW

OFF

ON

0

Bit 6

X

Reserved

Reserved

X

-

-

0

Bit 5

X

3V66(5:2) (See table 6)

Allow control of output with

assertion of CPU_STOP#.

XFreerun

Not

Freerun

0

Bit 4

X

3V66(1:0) (See table 7)

Allow control of output with

assertion of CPU_STOP#.

XFreerun

Not

Freerun

0

Bit 3

RW

-

-

0

Bit 2

RW

-

-

0

Bit 1

RW

-

-

0

Bit 0

RW

-

-

0

Note:

Pin #

Name

0

1

PWD

Bit 7

X

Revision ID Bit 3

R

-

-

0

Bit 6

X

Revision ID Bit 2

R

-

-

0

Bit 5

X

Revision ID Bit 1

R

-

-

0

Bit 4

X

Revision ID Bit 0

R

-

-

0

Bit 3

X

Vendor ID Bit 3

(Reserved)

R

-

-

0

Bit 2

X

Vendor ID Bit 2

(Reserved)

R

-

-

0

Bit 1

X

Vendor ID Bit 1

(Reserved)

R

-

-

0

Bit 0

X

Vendor ID Bit 0

(Reserved)

R

-

-

1

Affected Pin

BYTE

6

Functions in Byte 5 of CK408 were intended as a test and debug byte only.

00 = Medium (default), 01 = Low,

11,10 =High

Bit Control

Bit Control

Type

39

48MHz_USB Slew Control

48MHz_DOT Slew Control

38

BYTE

4

Affected Pin

BYTE

5

Control Function

Affected Pin

Bit Control

Type

BYTE

3

PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.

Control Function

Control Function

Type

Bit Control

00 = Medium (default), 01 = Low,

11,10 =High

Type

Control Function

Affected Pin

Revision ID Value Based on

Device Revision