Integrated

Circuit

Systems, Inc.

ICS950813

Advance Information

0708—10/10/02

Block Diagram

Recommended Application:

CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias

processor.

Output Features:

•

3 Differential CPU Clock Pairs @ 3.3V

•

7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks

•

3 PCI_F (3.3V) @ 33.3MHz

•

1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz

•

1 REF (3.3V) @ 14.318MHz

•

5 3V66 (3.3V) @ 66.6MHz

•

1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

Features:

•

Provides standard frequencies and additional 3%, 5%

and 10% over-clocked frequencies

•

Supports spread spectrum modulation:

No spread, Center Spread (±0.3%, ±0.55%), or Down

Spread (-0.5%, -0.75%)

•

Offers adjustable PCI early clock via latch inputs

•

Selectable 1X or 2X strength for REF via I

•

Programmable group to group skew

•

Linear programmable frequency and spreading %

•

Efficient power management scheme through PD#,

CPU_STOP# and PCI_STOP#.

•

Uses external 14.318MHz crystal

•

Stop clocks and functional control available through

I

Key Specifications:

•

CPU Output Jitter <150ps

•

3V66 Output Jitter <250ps

•

CPU Output Skew <100ps

Pin Configuration

Frequency Generator with 200MHz Differential CPU Clocks

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

VDDREF

1

56 REF

X1

2

55 FS1

X2

3

54 FS0

GND

4

53 CPU_STOP#*

PCICLK_F0

5

52 CPUCLKT0

PCICLK_F1

651 CPUCLKC0

*ASEL/PCICLK_F2

7

50 VDDCPU

VDDPCI

8

49 CPUCLKT1

GND

9

48 CPUCLKC1

PCICLK0 10

47 GND

**E_PCICLK1/PCICLK1 11

46 VDDCPU

PCICLK2 12

45 CPUCLKT2

**E_PCICLK3/PCICLK3 13

44 CPUCLKC2

VDDPCI 14

43 MULTSEL*

GND 15

42 IREF

PCICLK4 16

41 GND

PCICLK5 17

40 PWRSAVE#*

PCICLK6 18

VDD3V66 19

38 48MHz_DOT

GND 20

37 VDD48

3V66_2 21

36 GND

3V66_3 22

3V66_4 23

34 PCI_STOP#*

3V66_5 24

*PD# 25

32 VDD3V66

VDDA 26

31 GND

GND 27

30 SCLK

Vtt_PWRGD# 28

29 SDATA

56-Pin 300mil SSOP

56-Pin 240mil TSSOP

Functionality Table

CPU

AGP

PCI

MHz

MHz

MHz

0

0

100.00

66.67

33.33

0

1

133.33

66.67

33.33

10

200.00

66.67

33.33

11

166.66

66.66

33.33

FS1

FS0

PLL2

PLL1

Spread

Spectrum

3V66 (5:2)

48MHz_USB

48MHz_DOT

X1

X2

XTAL

OSC

3V66

DIVDER

PD#

Vtt_PWRGD#

PWRSAVE#

CPU_STOP#

PCI_STOP#

MULTSEL

SDATA

SCLK

FS (4:0)

I REF

Control

Logic

Config.

Reg.

REF

3V66_0

CPU

DIVDER

3

3

CPUCLKT (2:0)

CPUCLKC (2:0)

Stop

3V66_1/VCH_CLK

PCICLK (6:0)

PCI

DIVDER

3

7

PCICLK_F (2:0)

Stop

Asynchronous AGP/PCI Frequency Selection Table

Byte7 Bit5 Byte7 Bit4

AGP Frequency

PCI Frequency

0

0

66.00

33.00

0

1

75.43

37.72

1

0

88.00

44.00

1

1

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