Data Sheet

ADRF5141

THEORY OF OPERATION

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Rev. 0 | 10 of 13

The ADRF5141 integrates a driver to perform logic function inter-

nally and to provide the advantage of a simplified control interface.

The driver features a single-control input pin (CTRL) that controls

the state of the RF paths, determining which RF port is in an

insertion loss state and which RF port is in an isolation state (see

Table 6).

POWER SUPPLY

The ADRF5141 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect to ground.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp-up.

3. Power up the digital control input (CTRL). Power up CTRL be-

fore the VDD supply can inadvertently forward bias and damage

the internal ESD protection structures. To avoid this damage,

use a series 1 kΩ resistor to limit the current flowing into the

CTRL pin. Use pull-up or pull-down resistors if the controller

output is in a high-impedance state after VDD is powered up and

the CTRL pin is not driven to a valid logic state

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

RF INPUT AND OUTPUT

All RF ports (ANT, RX, and TX) are DC-coupled to 0 V. When the

RF line DC potential is at 0 V, no DC blocking is required at the RF

ports.

The RF ports are internally matched to 50 Ω; therefore, no external

matching networks are required.

Table 6. Control Voltage Truth Table

Digital Control Input

RF Paths

CTRL

TX to ANT

ANT to RX

Low

Insertion loss (on)

Isolation (off)

High

Isolation (off)

Insertion loss (on)