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www.diodes.com

April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

5.1 Interrupt mode operation

In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal,

IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced.

Figure 5 shows Interrupt mode operation.

5.2 Polled mode operation

In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the Line Status Register (LSR).

This mode is an alternative to the FIFO Interrupt mode of operation where the status of the receiver and transmitter is automatically

known by means of interrupts sent to the CPU. Figure 6 shows FIFO Polled mode operation.

read LSR

HOST

0

0 0 0

THR

RHR

LSR

IER

read IIR

HOST

1

1 1 1

THR

RHR

IIR

IER

IRQ

Figure 5. Interrupt mode operation

Figure 6. FIFO Polled mode operation