PI7C9X760ACLEX datasheet(28/53 Pages) DIODES

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April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

FIFO enable

0 = Disable the transmit and receive FIFO, and TX/RX can only hold one character at a time. Other

FCR bits are not programmable, and the trigger level is set to one character.

1 = enable the transmit and receive FIFO, and TX/RX FIFO can hold 64 characters.

Note: FCR[5:4] can only be modified and enabled if EFR[4]=1.

Offset 02H: Enhanced Feature Register (EFR). Accessible when LCR=0xBF and SFR[2]=0. Default=00

Bit

Type

Description

Auto CTS Flow Control Enable

0 = Automatic CTS flow control is disabled.

1 = Automatic CTS flow control is enabled.

Auto RTS Flow Control Enable

0 = Automatic RTS flow control is disabled.

1 = Automatic RTS flow control is enabled.

Special character detect

0 = Special character detect is disabled.

1 = Special character detect is enabled. If received data match Xoff2 data, the received data is trans-

ferred to RX FIFO and IIR[4] is set to high to indicate a special character detection.

However,if flow control is set for comparing Xoff2, then flow control works normally and Xoff2 will

not go to the FIFO and will generate an Xoff interrupt and a special character interrupt.

Enhanced Function Bits Enable

This bit enables IER[7:4],IIR[5:4],FCR[5:4],MCR[7:5],TCR and TLP to be modified, and enables the

sleep mode.

[3:0]

Software Flow Control Select:

00xx = No TX flow control

10xx = Transmit Xon1,Xoff1

01xx = Transmit Xon2,Xoff2

11xx = Transmit Xon1 and Xon2,Xoff1 and Xoff2

xx00 = No RX flow control

xx10 = Receiver compares Xon1,Xoff1

xx01 = Receiver compares Xon2,Xoff2

1011 = Transmit Xon1,Xoff1;

Receiver compares Xon1 or Xon2,Xoff1 or Xoff2

0111 = Transmit Xon2,Xoff2;

Receiver compares Xon1 or Xon2,Xoff1 or Xoff2

1111 = Transmit Xon1 and Xon2,Xoff1 and Xoff2;

Receiver compares Xon1 and Xon2,Xoff1 and Xoff2

0011 = No transmit flow control;

Receiver compares Xon1 and Xon2,Xoff1 and Xoff2

Offset 03H: Line Control Register (LCR). Default=1D

Bit

Type

Description

Divisor latch enabled when set

Configuration Registers cont..

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