8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

8

Integrated

Circuit

Systems, Inc.

ICS8745B

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

A general LVDS interface is shown in

Figure 2. In a 100

Ω differ-

ential transmission line environment, LVDS drivers require a

matched load termination of 100

Ω across near the receiver in-

put. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

100 Ohm Differiential Transmission Line

R1

100

3.3V

+

-

LVDS_Driv er

3.3V

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLKx

nCLKx

VDD