8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

9

Integrated

Circuit

Systems, Inc.

ICS8745B

3.3V

R1

50

R3

50

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

R2

50

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

R3

125

R2

84

Zo = 50 Ohm

3.3V

R4

125

LVPECL

R1

84

3.3V

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

V

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in

Figure 4A, the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

R2

50

Input

LVHSTL Driver

ICS

HiPerClockS

R1

50

LVHSTL

3.3V

Zo = 50 Ohm

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

R1

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8745B provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 3 illustrates how

a 10

Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V

10

Ω

V

DDA

10

μF

.01

μF

3.3V

.01

μF

V

DD