STMPE812 datasheet(22/51 Pages) STMICROELECTRONICS

22 / 51 page

Interrupt system

STMPE812

22/51

Doc ID 17732 Rev 3

ISR

Interrupt status register

Address:

0x0A

Type:

Reset:

0x00

Description:

ISR register monitors the status of the interruption from a particular interrupt source

to the host. Regardless whether the INT_EN bits are enabled, the ISR bits are still

updated.

Writing to this register has no effect. Reading the register clears any asserted bit

Implementation: A shadow register MUST be used to ensure that Read+Clear action

DOES NOT clear up any bit that is not READ.

Note: Reading the Interrupt Enable Register also clears the ISR. It is recommended that no read operation on IER

to be executed during normal operation. IER should only be accessed during initialization.

In PEN_DOWN interrupt mode, this status register is still updated with event interrupt status

data, and cleared on read. However no interrupt is issued based on this status register.

543

TSC_ERR

TSC_RELEASE

TSC_DATA

TSC_TOUCH

000

[7] TSC_ERR

Error encountered in coordinate calculation in TSC, or touch detect not valid after sampling

[6] TSC_RELEASE:

Release of touch is detected

[5] P3

Port 3 activity (GPIO)

[4] P2

Port 2 activity (GPIO)

[3] P1

Port 1 activity (GPIO/ADC/PWM)

[2] P0

Port 0 activity (GPIO/ADC)

[1] TSC_DATA

Touch data available. In internal timer and host-read controlled mode, this bit can only be

cleared after the data has been read by the host. In ACQ mode, this bit is cleared after the data

or the ISR is read by the host.

[0] TSC_TOUCH

Touch is detected.

(In PEN-DOWN interrupt mode, this bit is never cleared until pen is removed)

Obsolete

Product(s)

- Obsolete

Product(s)

STMPE812 数据表(PDF) 22 Page - STMicroelectronics

STMPE812 数据表(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载