STPM32TR datasheet(68/121 Pages) STMICROELECTRONICS

68 / 121 page

Theory of operation

STPM32, STPM33, STPM34

68/121

DS10272 Rev 8

Figure 48. Single communication time frame

Data and configuration registers are organized into 32-bit rows in the internal memory, but

can only be accessed 16-bit at a time for writing operations.

The address space is 70 rows wide, so there are 70 32-bit addressable elements for reading

operations; since the first 21 configuration registers are writable, there are 42 (= 21 x 2)

16-bit addressable elements for writing operations.

Figure 49. Memory data organization

Two different codes are used for the read address space and write address space, which

can be found in the register map.

8.6.1

Synchronization and remote reset functionality

Data into read-only registers are updated internally by DSP with frequency: 7.8125 kHz

(clock frequency measure). Latching is used to sample the updated results into transmission

latches. The transmission latches are flip-flops holding the data in the communication

interface.

Data latching can be implemented in three ways:



Using SYN and SCS pin



Writing the channel latch bits before each reading (S/W Latchx in DSP_CR3)



Writing auto-latch bit (S/W Auto Latch in DSP_CR3) to automatically latch data

registers every clock measure period (128 μs)

The remote reset can be performed in two ways:



Using SYN and SCS pin



Writing the reset bit (S/W reset in DSP_CR3)

STPM32TR 数据表(PDF) 68 Page - STMicroelectronics