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STPM32TR 数据表(PDF) 76 Page - STMicroelectronics |
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STPM32TR 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 121 page  Theory of operation STPM32, STPM33, STPM34 76/121 DS10272 Rev 8 SPI RX overrun: occurs when two consecutive write transactions are too fast and close to each other SPI TX underrun: occurs when a read-back operation (= write then read the same register) or latch/read is too fast SPI CRC error: CRC error detected UART/SPI write address error: write address out of range (not write address not writable) Table 33. UART/SPI status and interrupt control register Register Bit position Description Default value Access mode SR 30 SPI RX overrun 0 RW 29 SPI TX underrun 0 RW 28 SPI CRC error 0 RW 27 UART/SPI write address error 0 RW 26 UART/SPI read address error 0 RW 25 SPI TX empty 0 RO 24 SPI RX full 0 RO 22 UART TX overrun 0 RW 21 UART RX overrun 0 RW 20 UART noise error 0 RW 19 UART frame error 0 RW 18 UART timeout error 0 RW 17 UART CRC error 0 RW 16 UART break 0 RW IRQ CR 14 mask for SPI RX overrun error status bit 0 RW 13 mask for SPI TX underrun error status bit 0 RW 12 mask for SPI CRC error status bit 0 RW 11 mask for write address error status bit 0 RW 10 mask for read address error status bit 0 RW 9 mask for SPI TX empty 0 RW 8 mask for SPI RX full 0 RW 6 mask for UART TX overrun 0 RW 5 mask for UART RX overrun 0 RW 4 mask for UART noise error 0 RW 3 mask for UART frame error 0 RW 2 mask for UART timeout error 0 RW 1 mask for UART CRC error 0 RW |
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