STPM32TR datasheet(69/121 Pages) STMICROELECTRONICS

部件名	STPM32TR

功能描述	ASSP for metering applications with up to four independent 24-bit 2nd order sigma-delta ADCs, 4 MHz OSF and 2 embedded PGLNA

PDF	121 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

69 / 121 page

DS10272 Rev 8

69/121

STPM32, STPM33, STPM34

Theory of operation

121

SYN pin: latching, reset and global reset

Latching of internal memory registers can be carried out by producing pulses of a given

width on SYN pin while SCS line is high as depicted in Figure 50.

If a single pulse on SYN is detected, latch occurs.

If two consecutive pulses are detected, a reset of measurement registers occurs and the

counters are reset, as well.

If three consecutive pulses are detected, a global reset occurs, the configuration is also

reset and the chip must be initialized again.

Note:

To ensure a correct initialization of DSP, it is recommended to perform a global reset

through three SYN pulses at startup and before setting configuration bits.

Figure 50. Latching and reset through SYN pulses

Latch pulse width and other SPI timings are reported in Table 5 on page 17.

Figure 51. Latching through SYN pulses

Software latch

Writing S/W Latchx configuration bits of DSP_CR3 register can latch data into transmission

latches. These two bits latch channel 1 and channel 2 data registers respectively; once set,

they latch data and are automatically reset. By setting S/W Auto Latch bit, latching is

performed automatically at the rate of sampling clock, so data latching, before each reading

request, is no longer necessary.

STPM32TR 数据表(PDF) 69 Page - STMicroelectronics