FXPS7115D4 datasheet(35/75 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

TEMP[7:0]

Reset

Access

Table 45. TEMPERATURE - temperature register (address 0Eh) bit allocation

7.7.4 DEVLOCK_WR - lock register writes register (address 10h)

The lock register writes register is a read/write register that contains the ENDINIT bit and

reset control bits.

Bit

Symbol

ENDINIT

reserved

SUP_ERR_DIS

reserved

RESET[1:0]

Factory default

Access

R/W

Table 46. DEVLOCK_WR - lock register writes register (address 10h) bit allocation

Bit

Symbol

Description

ENDINIT

The ENDINIT bit is a control bit used to indicate that the user has completed all device and

system level initialization tests. Once the ENDINIT bit is set, writes to all writable register bits

are inhibited except for the DEVLOCK_WR register. Once set, the ENDINIT bit can only be

cleared by a device reset.

When ENDINIT is set, the following occurs:

• An error detection is enabled for all user writable registers. The error detection code is

continuously calculated on the user writable registers and verified against a previously

calculated error detection code.

• Self-test is disabled and inhibited.

• Register writes are inhibited except for the RESET[1:0] bits in the DEVLOCK_WR register.

SUP_ERR_DIS

The supply error disable bit allows the user to disable reporting of the supply errors in the SPI

status fields.

In SPI Mode:

• 0: No Response until the supply monitor timer expires. The Sensor Data Field Error Code

is transmitted for one response after the supply monitor timer expires. All supply errors

are cleared by a read of the DEVSTAT1 register through any communication interface or

on a data transmission that includes the error in the status field if and only if the timer has

reached zero.

• 1: No Responses occur if the timer is non-zero. The error is cleared when the timer reaches

zero and normal transmissions resume.

In I2C Mode (0 or 1):

• No response until the supply monitor timer expires.

• All supply errors are cleared by a read of the DEVSTAT1 register.

1 to 0 RESET[1:0]

To reset the device, three consecutive register write operations must be performed in the order

shown in Table 48, or the device will not reset.[1]

Table 47. DEVLOCK_WR - lock register writes register (address 10h) bit description

[1]

After POR and/or soft reset, see Section 7.5.5 for initialization sequence.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 6 June 2022

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