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AS1108PL 数据表(PDF) 3 Page - ams AG

部件名 AS1108PL
功能描述  4-Digit LED Display Driver
PDF  19 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1108PL 数据表(HTML) 3 Page - ams AG

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www.austriamicrosystems.com
Revision 2.1
3 - 19
AS1108
austriamicrosystems
Data Sheet
5 Electrical Characteristics
Conditions: VDD = 2.7 to 5.5V, RSET = 9.53k
Ω±1%, TAMB = TMIN to TMAX (unless otherwise specified).
Note: See Figure 9 on page 6 for additional timing information.
Table 2. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Supply Voltage
VDD
2.7
5.0
5.5
V
Shutdown Supply Current
IDDSD
All digital inputs at VDD or GND,
TAMB = +25ºC
10
µA
Operating Supply Current
IDD
RSET = open circuit.
1
mA
All segments and decimal point
on; ISEG = -40mA.
330
Display Scan Rate
fOSC
4 digits scanned
1000
1600 2600
Hz
Digit Drive Sink Current
IDIGIT
VOUT = 0.65V
320
mA
Segment Drive Source Current
ISEG
VDD = 5.0V, VOUT = (VDD -1V)
-30-40
-45mA
Segment Drive Current Matching
ΔISEG
3.0
%
Digit Drive Source Current
IDIGIT
Digit off, VDIGIT = (VDD - 0.3V)
-2
mA
Segment Drive Sink Current
ISEG
Segment off, VSEG = 0.3V
5mA
Slow Segment Blink Period (ON
phase, Internal Oscillator)
tSLOWBLINK
0.64
1
1.65
s
Fast Segment Blink Period
(ON phase, Internal Oscillator)
tFASTBLINK
0.32
0.5
0.83
s
Fast or Slow Segment Blink Duty
Cycle (Guaranteed by design)
49.9
50
50.1
%
Table 3. Logic Inputs/Outputs Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Current DIN, CLK, LOAD/CSN
IIH, IIL
VIN = 0V or VDD
-1
1
µA
Logic High Input Voltage
VIH
0.7 x VDD
V
Logic Low Input Voltage
VIL
VDD = 5.0V ± 10%
0.8
V
VDD = 3.0V ± 10%
0.6
Output High Voltage
VOH
DOUT, ISOURCE = -1mA,
VDD = 5.0V ± 10%
VDD - 1
V
DOUT, ISOURCE = -1mA,
VDD = 3.0V ± 10%
VDD - 0.5
Output Low Voltage
VOL
DOUT, ISINK = 1.6mA
0.4
V
Hysteresis Voltage
ΔVI
DIN, CLK, LOAD/CSN
1
V
Table 4. Timing Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CLK Clock Period
tCP
100
ns
CLK Pulse Width High
tCH
50
ns
CLK Pulse Width Low
tCL
50
ns
CSMFall-to-CLK Rise Setup Time
(AS1108 SPI-programmed)
tCSS
25
ns
CLK Rise-to -LOAD/CSN Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
25
ns
DIN Hold Time
tDH
0ns
Output Data Propagation Delay
tDO
CLOAD = 50pF
25
ns
LOAD Rising Edge-to-Next Clock Rising Edge
tLDCK
50
ns
Minimum LOAD/CSN Pulse High
tCSW
50
ns
Data-to-Segment Delay
tDSPD
2.25
ms



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