FT902L-R datasheet(29/67 Pages) BRIDGETEK

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FT900

/1/2/3 Revision C Embedded Microcontroller Datasheet

Version 1.0

Document No. BRT_000172 Clearance No.: BRT#087

4.14

I2C Interface

The FT900/1/2/3 series supports an I2C bus controller which is a bidirectional two wire interface. The two

wires are Serial Clock line (SCL) and Serial Data line (SDA). The interface can be programed to operate

with arbitration and clock synchronization allowing it to operate in multi-master systems. I2C0 and I2C1

support transmission speed up to 3.4Mb/s.

4.14.1

Features



Conforms to v2.1 and v3.0 of the I2C specification.

UM10204 I2C-bus specification and user manual Rev. 6 – 4 April 2014



Support flexible transmission speed modes:

Standard (up to 100 kb/s)

Fast (up to 400 kb/s)

Fast-plus (up to 1 Mb/s)

High-speed (up to 3.4 Mb/s)



One I2C Master and one I2C Slave interface with switchable pins are available.



Perform arbitration and clock synchronization.



Multi-master systems supported.



Support both 7-bit and 10-bit addressing modes on the I2C bus.



Support clock stretching.

4.15

UART Interface

The FT900/1/2/3 series contains two UART controllers with standard transmit and receive data lines.

UART0 provides a full modem control handshake interface and support for 9-bit data, allowing automatic

address detection while 9-bit data mode is enabled.

UART1 is a simplified programmable serial interface with CTS and RTS flow control logic. The signals are

multiplexed with UART0 and can only be used if UART0 is used in simple mode (CTS/RTS only).

4.15.1

Features



Maximum UART data bit rate of 8 Mb/s.



Support UART mode and FIFO mode operation.



16 / 128 bytes FIFO for TX and RX in FIFO mode to reduce the interrupt frequency.



Software compatible with 16450, 16550, 16750 and 16950 industry standard.



Modem control function (CTS, RTS, DSR, DTR, RI, and DCD) support for UART0.



Programmable automatic out-of- band flow control logic through Auto-RTS and Auto-CTS.



Programmable automatic flow control logic using DTR and DSR.



Programmable automatic in-band flow control logic using XON/XOFF characters.



Support external RS-485 buffer enable.



Fully programmable serial interface characteristics:

5-, 6-, 7-, 8-, or 9-bit data characters

Even, Odd, or No-parity bit generation and detection

1-, 1.5- or 2-stop bit generation

Baud rate generation

Detection of bad data in Receive FIFO



Support Transmitter and Receiver disable capability.

4.16

Timers and Watchdog Timer

The FT900/1/2/3 series has four 16-bit user timers with individual pre-scaler and a 32-bit watchdog

feature.

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