FT902L-R datasheet(33/67 Pages) BRIDGETEK

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FT900

/1/2/3 Revision C Embedded Microcontroller Datasheet

Version 1.0

Document No. BRT_000172 Clearance No.: BRT#087

4.24

System Clocks

4.24.1 12 MHz Oscillator

The oscillator generates a 12 MHz reference frequency output to the clock multiplier PLL. The oscillator

clock source comes from either an external 12 MHz crystal or a 12 MHz square wave clock. The external

crystal is connected across XI/CLKIN and XIO in the configuration shown in Section 6.1. The optional

external clock input is connected to XI/CLKIN only.

4.24.2 Phase Locked Loop

The internal PLL takes a 12 MHz clock input from a crystal oscillator. The PLL outputs the 100 MHz

system clock frequency to the CPU processor and other peripheral circuits. Each peripheral has an

individual enable control signal to gate the clock source.

4.24.3 32.768 KHz RTC Oscillator

The RTC oscillator provides a clock to the RTC time counter. Either an external 32.768 kHz crystal or a

32.768 kHz square wave clock can be used as the clock source. The external crystal is connected across

RTC_XI/RTC_CLKIN and RTC_XIO in the configuration shown in Section 6.2. The optional external clock

input is connected to RTC_XI/RTC_CLKIN only.

4.24.4 Internal Slow Clock Oscillator

The internal slow clock oscillator provides at least 5ms slow clock source to generate an interrupt for the

USB 2.0 device remote wake-up feature. A USB 2.0 device with remote wake-up capability may not

generate resume signalling unless the bus has been continuously in the idle state for 5ms. The detail

description for USB 2.0 suspend/resume, please refer to USB 2.0 specification chapters 7.1.7.6 and

7.1.7.7.

4.25

Power Management

4.25.1 Power Supply

The FT900/1/2/3 series may be operated with a single supply of +3.3V applied to VCCIO3V3, VUSB3V3,

VETH3V3 and VCC3V3A pins. The +1.2V internal regulator VOUT1 provides power to the core circuit after

VCCIO3V3 power on and the system will generate a Power on Reset (POR) pulse when the output voltage

rises above the POR threshold. VOUT1 also provides power to the internal PLL.

The second +1.2V internal regulator VOUT2 will provide the power to the Ethernet transceiver when

VETH3V3 gets the power supply.

4.25.2 Power Down Mode

Power down mode applies to the entire system. In the power down mode, the system 12-MHz oscillator

and PLL both switch off and the system clock to the core and all peripherals stop except for the RTC

oscillator and internal regulator. The internal regulator retains the power for the core and RTC running.

An interrupt from GPIO or wake-up events from the USB 2.0 device controller and host controller can

wake-up the system from the power down mode independently.

If the USB 2.0 host controller was used and the respective interrupt bit enabled before the system

entered into power down mode, then the following events can wake-up the system.



Remote wake-up interrupt to USB 2.0 host controller.



USB device connected interrupt to USB 2.0 host controller.

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