Si32172/3/5

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Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021

12.1. QFN PCB Design

1. PCB design must ensure sufficient thermal relief for high power operation of the device. See layout

guidelines in application note AN340 for further details.

2. A minimum of four vias are required under each E-Pad. Eight or more vias are recommended.

3. Via diameter should be between 0.20 and 0.31 mm.

4. Vias should either be filled or tented on the top side of the board to prevent solder thieving under the

device.

12.2. QFN Solder Mask Design

All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad

is to be 60 µm minimum, all the way around the pad.

12.3. QFN Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure

good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. A 1x2 array of 1.40 mm square openings on 1.7 mm pitch should be used for the top center pad and a 2x2

array of 1.35 mm square openings on 1.7 mm pitch should be used for the bottom center pad (as shown

below).

12.4. QFN Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body

Components.