48LM01 datasheet(2/40 Pages) MICROCHIP

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DS20006008C-page 2

48L512/48LM01

General Description

The Microchip Technology Inc. 48L512/48LM01

(48LXXX) serial EERAM has an SRAM memory core

with hidden EEPROM backup. The device can be

treated by the user as a full symmetrical read/write

SRAM. Backup to EEPROM is handled by the device

on any power disrupt, so the user can effectively view

this device as an SRAM that never loses its data.

The device is structured as a 512/1024-Kbit SRAM

with EEPROM backup in each memory cell. The

SRAM

organized

65,536 x 8

bits

131,072 x 8 bits, and uses the SPI serial interface.

The

SPI

bus

uses

three

signal

lines

for

communication: clock input (SCK), data in (SI), and

data out (SO). Access to the device is controlled

through a Chip Select (CS) input, allowing any number

of devices to share the same bus.

The SRAM is a conventional serial SRAM: it allows

symmetrical reads and writes and has no limits on cell

usage. The backup EEPROM is invisible to the user

and cannot be accessed by the user independently.

The device includes circuitry that detects VCC

dropping below a certain threshold, shuts its

connection to the outside environment, and transfers

all SRAM data to the EEPROM portion of each cell for

safe keeping. When VCC returns, the circuitry

automatically returns the data to the SRAM and the

user’s interaction with the SRAM can continue with the

same data set.

Block Diagram

Powering the Device During SRAM to

EEPROM Backup (VCAP)

A small capacitor (typically 47 μF to 100 μF) is required

for the proper operation of the device. This capacitor is

placed between VCAP (pin 3) and the system VSS (see

Normal Device Operation). When power is first applied

to the device, this capacitor is charged to VCC through

the device (see Normal Device Operation). During nor-

mal SRAM operation, the capacitor remains charged to

VCC and the level of system VCC is monitored by the

device. If system VCC drops below a set threshold, the

device interprets this as a power-off or brown-out

event. The device suspends all I/O operation, shuts off

its connection with the VCC pin, and uses the saved

energy in the capacitor to power the device through the

VCAP pin as it transfers all SRAM data to EEPROM

(see Vcc Power-Off Event). On the next power-up of

VCC, the data is transfered back to SRAM, the capaci-

tor is recharged, and the SRAM operation continues.

Normal Device Operation

VCC Power-Off Event

Power

SPI Control Logic

Memory Address

and Data Control

Logic

and Address

VCC

Control

Block

VCAP

Decoder

EEPROM

128K x 8

RECALL

STORE

SCK

64K x 8

SRAM

128K x 8

64K x 8

HOLD

STATUS

CC Monitor

Normal

SRAM

Operation

CC (pin 8)

CAP (pin 3)

VCAP

Charged to V

SS (pin 4)

System V

SCK

HOLD

System V

Automatic

Backup

SRAM

SRAM to

EEPROM

Transfer

EEPROM

CC (pin 8)

System V

SCK

HOLD

CAP (pin 3)

VCAP

Temporary V

SS (pin 4)

System V

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