48LM01 datasheet(21/40 Pages) MICROCHIP

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DS20006008C-page 21

48L512/48LM01

10.0 SECURE OPERATIONS

The 48LXXX devices support secure write and read

operations, which add another layer of protection to

data. The secure write and read operations use a CRC

checksum on a fixed number of bytes and the address

bits, to be sure the data beginning at that address

matches the given checksum before it is considered

valid.

The 512 Kbit uses a 64-byte, and 1 Mbit device uses a

128-byte, and address CRC calculation. The devices

accept or transmit a 2-byte CRC value calculated from

the SRAM data and address bits. Only valid address

bits are used in the calculation (upper address bits that

extend beyond the array size are ignored in the CRC

calculation). The range of the secure write and read

operations is limited to the exact number of bytes

within the 64-byte or 128-byte page boundary.

10.1

Secure Write

To enable the secure write operation, a WEL bit has to

be set first. The CS line is set low, the Secure Write

command is sent, followed by the address bytes.

Only the valid address bits are used in the CRC

calculation (see Table 10-1 below). Then, data is sent

to the required number of bytes, and the expected

CRC value is calculated internally as bytes are sent in.

After the last byte is written, the 16-bit CRC is to be

clocked in on SI, then the CS pin is set high.

The CRC16-CCITT polynomial used is x16+x12+x5+1.

The boundary for the write operation should align with

the size of the range, 64 bytes for 512K device, and

128 bytes for 1M device. It is possible to write to an

address that does not begin at the page boundary, but

the address pointer will roll-over from the end of the

page to the beginning and the required checksum

bytes will likely be different.

The initial value for the CRC calculation is 0xFFFF.

The checksum must be transmitted with MSb first. In

addition, the internally calculated CRC has to match

the transmitted CRC. If they match, the data will be

accepted and written to the array. If the CRC values do

not match, data will be ignored and the existing

memory data will stay as it was and the SWM bit in the

STATUS register will be set to ‘1’, indicating a secure

write error. The status of the SWM bit should be read

after every secure write operation to confirm the

operation was successful. The SWM bit in the

STATUS register is read-only and will automatically

reset to ‘0’ at the beginning of the next secure write

operation.

With the low-to-high transition of the CS pin, the

device is automatically returned to the Write Disable

state, with the WEL bit returning to ‘0’.

10.2

Secure Read

The secure read operation requires the CS pin to be

brought low and the secure read opcode sent in on the

SI pin. Following that is the address (2 or 3 bytes,

depending on device). The valid address bits are part

of the CRC calculation. Only the correct number of bits

can be read, which are 64 or 128 bytes, depending on

the device, clocked out on the SO pin (see Table 10-1

for details). As the data is sent out, a CRC checksum

is calculated. The CRC16-CCITT polynomial used is

x16+x12+x5+1. After the data bytes are sent, then the

two CRC bytes are sent, and the master sets the CS

pin high to finish the operation. The master reading the

SRAM can do a CRC calculation to confirm that the

address and data agree with the checksum bytes

provided by the device.

The secure read should align with a SRAM address

boundary of 64 bytes for 512K device or 128 bytes for

1M device. It is possible to read from an address that

does not begin at the page boundary, but the address

pointer will roll-over from the end of the page to the

beginning and the checksum bytes read will likely be

different.

The SWM bit in the STATUS register is not affected by

secure read operations.

TABLE 10-1:

SECURE WRITE BITS

Device

Address

Bytes

Address

Bits

Data

Bytes

Required

CRC

Bits

48L512

48LM01

128

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