48LM01 datasheet(10/40 Pages) MICROCHIP

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DS20006008C-page 10

48L512/48LM01

4.0

FUNCTIONAL DESCRIPTION

The 48L512/48LM01 is controlled by a set of

instructions that are sent from a host controller,

commonly referred to as the SPI Master. The SPI

Master communicates with the 48L512/48LM01 via the

SPI bus which is comprised of four signal lines:

• Chip Select (CS)

• Serial Clock (SCK)

• Serial Input (SI)

• Serial Output (SO)

The SPI protocol defines a total of four modes of

operation (Mode 0, 1, 2, or 3) with each mode differing

in respect to the SCK polarity and phase and how the

polarity and phase control the flow of data on the SPI

bus.

The 48L512/48LM01 supports the two most common

modes, SPI Modes 0 and 3. With SPI Modes 0 and 3,

data is always latched in on the rising edge of SCK

and always output on the falling edge of SCK. The

only difference between SPI Modes 0 and 3 is the

polarity of the SCK signal when in the inactive state

(when the SPI Master is in Standby mode and not

transferring any data). SPI Mode 0 is defined as a low

SCK while CS is not asserted (high) and SPI Mode 3

has SCK high in the inactive state. The SCK Idle state

must match when the CS is deasserted both before

and after the communication sequence in SPI Mode 0

and 3.

The figures in this document depict Mode 0 with a

solid line on SCK while CS is inactive and Mode 3 with

a dotted line.

FIGURE 4-1:

SPI MODE 0 AND MODE 3

4.1

Interfacing the 48L512/48LM01 on

the SPI Bus

Communication to and from the 48L512/48LM01 must

be initiated by the SPI Master device. The SPI Master

device must generate the serial clock for the

48L512/48LM01 on the SCK pin. The 48L512/48LM01

always operates as a slave due to the fact that the

Serial Clock pin (SCK) is always an input.

4.1.1

SELECTING THE DEVICE

The 48L512/48LM01 is selected when the CS pin is

low. When the device is not selected, data will not be

accepted via the SI pin and the SO pin will remain in a

high-impedance state.

4.1.2

SENDING DATA TO THE DEVICE

The 48L512/48LM01 uses the Serial Data Input (SI) pin

to receive information. All instructions, addresses, and

data input bytes are clocked into the device with the

Most Significant bit (MSb) first.

The SI pin samples on the first rising edge of the SCK

line after the CS has been asserted.

4.1.3

RECEIVING DATA FROM THE

DEVICE

Data output from the device is transmitted on the Serial

Data Output (SO) pin with the MSb output first. The SO

data is latched on the falling edge of the first SCK clock

cycle after the instruction has been clocked into the

device, such as the Read from Memory Array and

Read STATUS Register instructions. See Section 6.0

"STATUS Register" for more details.

Mode 3

Mode 0

Mode 3

Mode 0

MSb

LSb

SCK

MSb

LSb

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