LTC3313JVPBF datasheet(17/28 Pages) AD

17 / 28 page

LTC3313

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Applying a load transient and monitoring the response of

the system or using a network analyzer to measure the

actual loop response are two ways to verify and optimize

the control loop stability. LTpowerCAD® is a useful tool to

help optimize the compensation components.

When using the load transient response method to sta-

bilize the control loop, apply an output current pulse of

20% to 100% of the full load current having a rise time

of 1µs. This will produce a transient on the output voltage

and ITH pin waveforms.

Switching regulators take multiple cycles to respond to

a step in load current. When a load step occurs, VOUT is

immediately perturbed, generating a feedback error signal

used by the regulator to return VOUT to its steady-state value.

During this recovery time, monitor VOUT for overshoot

or ringing that would indicate a stability problem. The

initial output voltage step may not be within the band-

width of the feedback loop, so the standard second-order

overshoot/DC ratio cannot be used to determine phase

margin. The gain of the loop increases with RC and the

bandwidth of the loop increases with decreasing CC. If RC

is increased by the same factor that CC is decreased, the

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

feedback loop. In addition, adding a feedforward capaci-

tor, CFF, improves the high frequency response. Capacitor

CFF provides phase lead by creating a high frequency zero

with RA to improve the phase margin. The compensation

components of the typical application circuits are a good

starting point for component values.

The output voltage settling behavior is related to the sta-

bility of the closed-loop system. For a detailed explanation

of optimizing the compensation components, including

a review of control loop theory, refer to Analog Devices

Application Note 76.

Output Overvoltage Protection

During an output overvoltage event, when the FB node

voltage is greater than 110% of nominal, the LTC3313

top power switch will be turned off. If the output remains

out of regulation for more than 125µs, the PGOOD pin

will be pulled low.

An output overvoltage event should not happen under

normal operating conditions.

Output Voltage Sensing

The LTC3313 AGND pin is the ground reference for the

internal analog circuitry, including the bandgap voltage

reference. To achieve good load regulation, connect the

AGND pin to the negative terminal of the output capaci-

tor (COUT) at the load. A drop in the high current power

ground return path will be compensated. All of the signal

components, such as the FB resistor dividers and soft-

start capacitor, should be referenced to the AGND node.

The AGND node carries very little current and, therefore,

can be a minimal size trace. See the example PCB Layout

for more information.

Enable Threshold Programming

The LTC3313 has a precision enable pin threshold

to enable or disable switching. When forced low, the

LTC3313 enters a low current shutdown mode.

The rising threshold of the EN comparator is 400mV, with

60mV of hysteresis. Connect the EN pin to VIN if the shut-

down feature is not used. Adding a resistor divider from

VIN to EN programs the LTC3313 to regulate the output

only when VIN is above a desired voltage (see the Block

Diagram). Typically, this threshold, VIN(EN), is used in situ-

ations where the input supply is current limited or has a

relatively high source resistance. A switching regulator

draws constant power from the source, so source current

increases as source voltage drops. This looks like a nega-

tive resistance load to the source and can cause the source

to current limit or latch low under low source voltage

LTC3313JVPBF 数据表(PDF) 17 Page - Analog Devices

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