LTC3313JVPBF datasheet(19/28 Pages) AD

19 / 28 page

LTC3313

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 3. Soft-Start and Temperature Monitor Operation

DIE TEMP

(°C)

(V)

150

0.1

125

0.6

0.3

100

0.5

0.4

0.2

0.5

1.5

0.6

1.6

0.3

1.3

3313 F03

1.7

0.4

1.4

0.2

1.2

0.1

SSTT (V)

TEMP

MONITOR

~4mV/°C

SSTT PIN VOLTAGE

OPERATING RANGE

SOFT-START

AND TRACKING

When the output voltage goes out of regulation and the

power good pin is pulled low, the soft-start pin no longer

reports the temperature.

Output Power Good

When the LTC3313’s output voltage is within the –2/+10%

window of the nominal regulation voltage the output is

considered good. The open-drain PGOOD pin goes high

impedance and is typically pulled high with an external

resistor. Otherwise, the internal pull-down device will pull

the PGOOD pin low. To prevent glitching, both the upper

and lower thresholds include 1% of hysteresis as well as a

built-in time delay, typically 125µs. The PGOOD pin is also

actively pulled low during fault conditions: EN pin is low,

VIN is too low, or in thermal shutdown.

For multiphase applications the PGOOD pin is used for

communication between the master and slave phases.

Connect the PGOOD pins together and pull-up to VIN or

VOUT with an external resistor.

Output Short Circuit Protection and Recovery

The peak inductor current at which the current compara-

tor shuts off the top power switch is controlled by the

voltage on the ITH pin. If the output current increases,

the error amplifier raises the ITH pin voltage until the

average inductor current matches the new load current.

In normal operation, the LTC3313 clamps the maximum

ITH pin voltage.

When the output is shorted to ground, the inductor cur-

rent decays very slowly during the switch off time because

of the low voltage across the inductor. To keep the current

in control, a secondary limit is also imposed on the valley

inductor current. If the inductor current measured through

the bottom power switch stays above IVALLEY(MAX), the

top power switch will be held off and switching cycles will

be skipped until the inductor current is reduced.

Recovery from a short circuit can be abrupt and because

the output is shorted and below regulation the regulator

is requesting the maximum current to charge the output.

When the short circuit condition is removed, the induc-

tor current could cause an extreme voltage overshoot in

the output. The LTC3313 addresses this potential issue

by regulating the SSTT voltage just above the FB volt-

age anytime the output is out of regulation. Therefore,

a recovery from an output short circuit goes through a

soft-start cycle. The output ramp is controlled and the

overshoot is minimized.

Low EMI PCB Layout

The LTC3313 is specifically designed to minimize EMI/

EMC emissions and also to maximize efficiency when

switching at high frequencies. For optimal performance,

the LTC3313 requires the use of multiple VIN bypass

capacitors.

Many designs will benefit from additional 0.1μF, 0201

ceramic capacitors placed between the larger bulk input

ceramic capacitors and the IC. If the additional 0.1μF

capacitors are not added to the layout then the bulk input

ceramic capacitors should be moved as close as to the VIN

pin as possible.

To avoid noise coupling into the LTC3313 FB node, the

resistor divider should be placed near the FB and AGND

pins and physically close to the IC. The remote output

and ground traces should be routed together as a differ-

ential pair to the remote output. These traces should be

terminated as close as physically possible to the remote

output point that is to be accurately regulated through

remote differential sensing.

LTC3313JVPBF 数据表(PDF) 19 Page - Analog Devices

LTC3313JVPBF 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载