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TDA4VE...ALZQ1 数据表(PDF) 96 Page - Texas Instruments |
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TDA4VE...ALZQ1 数据表(HTML) 96 Page - Texas Instruments |
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96 / 251 page  Table 6-117. Connectivity Requirements BALL NUMBER BALL NAME CONNECTION REQUIREMENT H28 WKUP_OSC0_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level, if unused. M28 OSC1_XI B28 TRSTN L25 MCU_ADC0_AIN0 K25 MCU_ADC0_AIN1 M24 MCU_ADC0_AIN2 L24 MCU_ADC0_AIN3 L27 MCU_ADC0_AIN4 K24 MCU_ADC0_AIN5 M27 MCU_ADC0_AIN6 M26 MCU_ADC0_AIN7 P25 MCU_ADC1_AIN0 R25 MCU_ADC1_AIN1 P28 MCU_ADC1_AIN2 P27 MCU_ADC1_AIN3 N25 MCU_ADC1_AIN4 P26 MCU_ADC1_AIN5 N26 MCU_ADC1_AIN6 N27 MCU_ADC1_AIN7 G1 DDR0_DQS0P L1 DDR0_DQS1P V1 DDR0_DQS2P AB1 DDR0_DQS3P A16 DDR1_DQS0P A13 DDR1_DQS1P A6 DDR1_DQS2P A3 DDR1_DQS3P T8 DDR0_RET J10 DDR1_RET H23 VMON1_ER_VSYS L18 VMON6_IR_VEXT0P8 L22 VMON3_IR_VEXT1P8 M18 VMON2_IR_VCPU N19 VMON4_IR_VEXT1P8 N20 VMON5_IR_VEXT3P3 AC10 SERDES0_REXT Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level, if unused. Refer to Signal Descriptions footnote for appropriate value of pull-resistor for each signal. AC18 CSI0_RXRCALIB AC21 CSI1_RXRCALIB R8 DDR0_CAL0 E8 DDR1_CAL0 AC13 DSI0_TXRCALIB AC15 DSI1_TXRCALIB AA6 USB0_RCALIB TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 96 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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