TDA4VE...ALZQ1 datasheet(2/251 Pages) TI

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Video acceleration:

• TDA4VE: H.264/H.265 Encode/Decode (up to 480

MP/s)

• TDA4AL: H.264/H.265 Encode only (up to 480

MP/s)

• TDA4VL: H.264/H.265 Encode/Decode (up to 240

MP/s)

Ethernet:

• Two RMII/RGMII interfaces

Flash memory interfaces:

• Embedded MultiMediaCard Interface ( eMMC™

5.1)

• One Secure Digital® 3.0/Secure Digital Input

Output 3.0 interfaces (SD3.0/SDIO3.0)

• Two simultaneous flash interfaces configured as

– One OSPI or HyperBus™ or QSPI, and

– One QSPI

System-on-Chip (SoC) architecture:

• 16-nm FinFET technology

• 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA

(ALZ)

Companion Power Management ICs (PMIC):

• Functional Safety-Compliant support up to ASIL-

D / SIL-3 targeted

• Flexible mapping to support different use cases

2 Applications

• Advanced Driver Assistance System (ADAS)

• Machine vision

• Industrial transport

• Retail automation

• Surveillance

3 Description

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted

at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade

of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both

traditional and deep learning algorithms at industry leading power/performance ratios with a high level of

system integration to enable scalability and lower costs for advanced vision camera applications. Key cores

include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm

accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging

subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security

hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and

EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling

backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning

accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating

at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators

provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm®

Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm®

Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72

core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes

flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics

applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the

integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To

further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need

for an external system microcontroller.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1

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