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TDA4VE...ALZQ1 数据表(PDF) 164 Page - Texas Instruments |
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TDA4VE...ALZQ1 数据表(HTML) 164 Page - Texas Instruments |
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164 / 251 page  The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1), GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general purpose interface supports up to 248 I/O pins. For more details about features and additional description information on the device General-Purpose Interface, see the corresponding sections within Signal Descriptions and Detailed Description. Note The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi. Table 7-38, Section 7.10.5.9.1, and Section 7.10.5.9.2 present timing conditions, requirements, and switching characteristics for GPIO. Table 7-38. GPIO Timing Conditions PARAMETER BUFFER TYPE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate LVCMOS 0.2 6.6 V/ns I2C OD FS 0.2 0.8 V/ns OUTPUT CONDITIONS CL Output load capacitance LVCMOS 3 10 pF I2C OD FS 3 100 pF 7.10.5.9.1 GPIO Timing Requirements NO. BUFFER TYPE MIN MAX UNIT GPIO1 tw(gpio_in) Pulse width, GPIOn_x 1.8 V 2P + 2.6(1) ns 3.3 V 2P + 3.4(1) ns (1) P = functional clock period in ns. 7.10.5.9.2 GPIO Switching Characteristics NO. PARAMETER BUFFER TYPE MIN MAX UNIT GPIO3 tw(GPIO_OUT) Minimum Output Pulse Width LVCMOS –3.6 + 0.975P(1) ns GPIO4 tw(GPIO_OUT) Minimum Output Pulse Width Low I2C Open Drain 160 ns GPIO5 tw(GPIO_OUT) Minimum Output Pulse Width High I2C Open Drain 60 ns (1) P = functional clock period in ns. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM. 7.10.5.10 GPMC For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding sections within Signal Descriptions and Detailed Description. Table 7-39 represents GPMC timing conditions. Note The IO timings provided in this section are applicable for all combinations of signals for GPMC0. However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs are defined in the GPMC0_IOSET, GPMC0_IOSET table. TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 164 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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