T48C862M-R3 datasheet(83/107 Pages) ATMEL

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T48C862-R3

4554A–4BMCU–02/03

Figure 80. FSK Modulation

Combination Mode 7:

Pulse-width Modulation

(PWM)

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects which compare register is used for the output pulse generation. In this

mode, both compare and compare mode registers must be programmed to generate the

two pulse width. It is also useful to enable the single-action mode for extreme duty

cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.

The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an

internal or external clock source.

Figure 81. Pulse-width Modulation

Combination Mode 8:

Manchester

Demodulation/Pulse-width

Demodulation

SSI mode 1:

8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3

For Manchester demodulation, the edge detection stage must be programmed to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage is used to generate the shift clock for the SSI. A compare register 1 match event

defines the correct moment for shifting the state from the input T3I as the decoded bit

into shift register. After that, the demodulator waits for the next edge to synchronize the

timer by a reset for the next bit. The compare register 2 can be used to detect a time

error and handle it with an interrupt routine.

0 1 23 40 123 401 20

Counter 3

CM31

CM32

12 012 01 20 12 01 2 0 12 01 20 1234 0

T3R

T3O

000 00 00 00

000 0

Counter 3

CM31

CM32

T3O

00 0 001 234 56 7 8 9 1011121314150 12 345

TOG2

67 8

91112

2 3

SIR

SCO

T3R

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