T48C862M-R3 datasheet(51/107 Pages) ATMEL

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T48C862-R3

4554A–4BMCU–02/03

Timer 2 Mode Register 1

(T2M1)

Address: "7"hex - Subaddress: "1"hex

Duty Cycle Generator

The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at

the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler

setting. The DCG-stage can also be used as additional programmable prescaler for

Timer 2.

Bit 3Bit 2Bit 1Bit 0

T2D1

T2D0

T2MS1

T2MS0

Reset value: 1111b

T2D1

Timer 2 Duty cycle bit 1

T2D0

Timer 2 Duty cycle bit 0

T2D1

T2D0

Function of Duty Cycle Generator (DCG)

Additional Divider Effect

Bypassed (DCGO0)

Duty cycle 1/1 (DCGO1)

Duty cycle 1/2 (DCGO2)

Duty cycle 1/3 (DCGO3)

T2MS1

Timer 2 Mode Select bit 1

T2MS0

Timer 2 Mode Select bit 0

Mode

T2MS1

T2MS0

Clock Output (POUT)

Timer 2 Modes

4-bit counter overflow (OVF1)

12-bit compare counter; the

DCG has to be bypassed in

this mode

4-bit compare output (CM1)

8-bit compare counter with

4-bit programmable prescaler

and duty cycle generator

4-bit compare output (CM1)

8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler run,

the counter 2/1 starts after

writing mode 3

4-bit compare output (CM1)

8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler stop

and resets

T48C862M-R3 数据表(PDF) 51 Page - ATMEL Corporation

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