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IXDN430 / IXDI430 / IXDD430 / IXDS430

IXYS Semiconductor GmbH

Edisonstrasse15 ; D-68623; Lampertheim

Tel: +49-6206-503-0; Fax: +49-6206-503627

e-mail: marcom@ixys.de

IXYS Corporation

3540 Bassett St; Santa Clara, CA 95054

Tel: 408-982-0700; Fax: 408-496-0670

www.ixys.com

e-mail: sales@ixys.net

OUTPUTLEADINDUCTANCE

Of equal importance to Supply Bypassing and Grounding are

issues related to the Output Lead Inductance. Every effort

should be made to keep the leads between the driver and it’s

load as short and wide as possible. If the driver must be placed

farther than 2” from the load, then the output leads should be

treated as transmission lines. In this case, a twisted-pair

should be considered, and the return line of each twisted pair

should be placed as close as possible to the ground pin of the

driver, and connect directly to the ground terminal of the load.

A TTL high, V

V

Figure 29 will cause Q1 to be biased off. This results in Q1

collector being pulled up by R3 to V

high voltage CMOS logic high output. The high voltage CMOS

logical EN output applied to the IXDD430 EN input will enable

it, allowing the gate driver to fully function as an 30 Amp

output driver.

The total component cost of the circuit in Figure 29 is less

than $0.10 if purchased in quantities >1K pieces. It is

recommended that the physical placement of the level

translator circuit be placed close to the source of the TTL or

CMOS logic circuits to maximize noise rejection.

Figure 29 - TTL to High Voltage CMOS Level Translator

TTL to High Voltage CMOS Level Translation

(IXDD430 Only)

The enable (EN) input to the IXDD430 is a high voltage

CMOS logic level input where the EN input threshold is ½

V

levels. The IXDD430 EN input was intentionally designed

for enhanced noise immunity with the high voltage CMOS

logic levels. In a typical gate driver application, V

and the EN input threshold at 7.5V, a 5V CMOS logical high

input applied to this typical IXDD430 application’s EN input

will be misinterpreted as a logical low, and may cause

undesirable or unexpected results. The note below is for

optional adaptation of TTL or 5V CMOS levels.

A TTL or 5V CMOS logic low, V

Q1 emitter will drive it on. This causes the level translator

output, the Q1 collector output to settle to V

V

as a high voltage CMOS logic low (<1/3V

in the IXDD430 data sheet.)

The circuit in Figure 29 alleviates this potential logic level

misinterpretation by translating a TTL or 5V CMOS logic

input to high voltage CMOS logic levels needed by the

IXDD430 EN input. From the figure, V

power supply, typically set between 8V to 20V, and V

the logic power supply, typically between 3.3V to 5.5V.

Resistors R1 and R2 form a voltage divider network so

that the Q1 base is positioned at the midpoint of the

expected TTL logic transition levels.

Q1

2N3904

R1

10K

R2

10K

R3

10K

Vdd

EN

power supply)

power supply)

5V CMOS or TTL input

(From logic

(To IXDD430 EN input)

CMOS EN output

High Voltage