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UPSD3422 数据表(PDF) 21 Page - STMicroelectronics |
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UPSD3422 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 Description 21/300 Figure 1. Block diagram PA0:7 PB0:7 PD1:2 PC0:7 MCU bus P4.0:7 P1.0:7 P3.0:7 uPSD34xx Dedicated pins Supervisor: Watchdog and low-voltage reset 1st Flash memory: 64 Kbyte, 128 Kbyte or 256 Kbyte 2nd Flash memory: 32 Kbyte SRAM: 4 Kbyte, 8 Kbyte or 32 Kbyte Programmable decode and page logic General- purpose programmable logic, 16 macrocells (8) GPIO, Port A (80-pin only) (8) GPIO, Port B (4) GPIO, Port C (2) GPIO, Port D JTAG ICE and ISP 8032 Address/Data/Control bus (80-pin device only) V CC, VDD, GND, Reset, Crystal In Turbo 8032 Core PFQ & BC (3) 16-bit Timer/ Counters (2) External Interrupts I 2C SPI (8) 10-bit ADC UART0 (8) GPIO, Port 1 (8) GPIO, Port 3 (8) GPIO, Port 4 USB+, USB– USB v2.0, Full Speed 10 FIFOs UART1 Optional IrDA Encoder/Decoder 16-bit PCA (6) PWM, CAPCOM, timer AI09695c Obsolete Product(s) - Obsolete Product(s) |
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