DS11873 Rev 5

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VIPer11

General description

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5.12

Max. duty cycle counter protection

The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is turned

off by max. duty cycle (70% min., 80% max.) for ten consecutive switching cycles. After

protection tripping, the PWM is stopped for tRESTART and then activated again with soft- start

phase until the fault condition is removed.

In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be

triggered because at every switching cycle the PWM is turned off by maximum duty cycle

before than DRAIN peak current reaches the IDLIM setpoint. As a result, the output voltage

VOUT can increase without control by keeping a value much higher than the nominal one

with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle

counter protection avoids this kind of failures.

5.13

VCC clamp protection

This protection can occur when the IC is supplied by auxiliary winding or diode from the

output voltage, when an output overvoltage produces an increase of VCC.

If VCC reaches the clamp level VCCclamp (30 V, min. referred to GND) the current injected

into the pin is monitored and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for

more than tclamp_max (500 μs, typ.), the PWM is disabled for tRESTART (1 s, typ.) and then

activated again in soft-start phase. The protection is disabled during the soft-start time.