Data Sheet

ADRF5050

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 13 of 14

The ADRF5050 has two power supply pins (VDD and VSS) and

four control pins (LS, EN, V1, and V2). Figure 26 shows the

external components and connections for the supply and control

pins. The supply and control pins are decoupled with 100 pF

multilayer ceramic capacitor. Place the decoupling capacitors as

close as possible to the ADRF5050. The device pinout allows the

placement of the decoupling capacitors close to the ADRF5050.

No other external components are needed for bias and operation,

except DC blocking capacitors on the RFx pins when the RF lines

are biased at a voltage different than 0 V. Refer to Pin Configuration

and Function Descriptions section for details.

Figure 26. Recommended Schematic

RECOMMENDATIONS FOR PRINTED CIRCUIT

BOARD DESIGN

The RF ports are matched to 50 Ω internally and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50 Ω char-

acteristic impedance on the PCB. Figure 27 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003 dielectric material. RF trace with 14 mil width and 7 mil

clearance is recommended for 1.5 mil finished copper thickness.

Figure 27. Example PCB Stack Up

Figure 28 shows the routing of the RF traces, supply, and control

signals from the ADRF5050. The ground planes are connected with

as many filled, through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 28. PCB Routings

Figure 29 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width by 2 mils

and tapered to RF trace with 45° angle. The paste mask is also

designed to match the pad without any aperture reduction. The

paste is divided into multiple openings for the paddle.

Figure 29. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, contact Analog Devices, Inc., Technical Support

Request for further recommendations.