LSM6DSO datasheet(165/172 Pages) STMICROELECTRONICS

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Table 106. FSM_STATUS_A_MAINPAGE register description ............................................ 69

Table 107. FSM_STATUS_B_MAINPAGE register .................................................... 70

Table 108. FSM_STATUS_B_MAINPAGE register description ............................................ 70

Table 109. STATUS_MASTER_MAINPAGE register................................................... 70

Table 110. STATUS_MASTER_MAINPAGE register description .......................................... 70

Table 111. FIFO_STATUS1 register .............................................................. 71

Table 112. FIFO_STATUS1 register description ...................................................... 71

Table 113. FIFO_STATUS2 register .............................................................. 71

Table 114. FIFO_STATUS2 register description ...................................................... 71

Table 115. TIMESTAMP output registers .......................................................... 72

Table 116. TIMESTAMP output register description ................................................... 72

Table 117. TAP_CFG0 register ................................................................. 73

Table 118. TAP_CFG0 register description ......................................................... 73

Table 119. TAP_CFG1 register ................................................................. 74

Table 120. TAP_CFG1 register description ......................................................... 74

Table 121. TAP priority decoding ................................................................ 74

Table 122. TAP_CFG2 register ................................................................. 74

Table 123. TAP_CFG2 register description ......................................................... 74

Table 124. TAP_THS_6D register ............................................................... 75

Table 125. TAP_THS_6D register description ....................................................... 75

Table 126. Threshold for D4D/D6D function ........................................................ 75

Table 127. INT_DUR2 register.................................................................. 76

Table 128. INT_DUR2 register description ......................................................... 76

Table 129. WAKE_UP_THS register.............................................................. 76

Table 130. WAKE_UP_THS register description ..................................................... 76

Table 131. WAKE_UP_DUR register ............................................................. 77

Table 132. WAKE_UP_DUR register description ..................................................... 77

Table 133. FREE_FALL register ................................................................ 78

Table 134. FREE_FALL register description ........................................................ 78

Table 135. Threshold for free-fall function .......................................................... 78

Table 136. MD1_CFG register .................................................................. 79

Table 137. MD1_CFG register description.......................................................... 79

Table 138. MD2_CFG register .................................................................. 80

Table 139. MD2_CFG register description.......................................................... 80

Table 140. I3C_BUS_AVB register ............................................................... 81

Table 141. I3C_BUS_AVB register description....................................................... 81

Table 142. INTERNAL_FREQ_FINE register........................................................ 81

Table 143. INTERNAL_FREQ_FINE register description................................................ 81

Table 144. INT_OIS register ................................................................... 82

Table 145. INT_OIS register description ........................................................... 82

Table 146. CTRL1_OIS register................................................................. 83

Table 147. CTRL1_OIS register description......................................................... 83

Table 148. DEN mode selection................................................................. 83

Table 149. CTRL2_OIS register................................................................. 84

Table 150. CTRL2_OIS register description......................................................... 84

Table 151. Gyroscope OIS chain digital LPF1 filter bandwidth selection ..................................... 84

Table 152. CTRL3_OIS register................................................................. 85

Table 153. CTRL3_OIS register description......................................................... 85

Table 154. Accelerometer OIS channel full-scale selection .............................................. 85

Table 155. Accelerometer OIS channel bandwidth and phase ............................................ 85

Table 156. Self-test nominal output variation ........................................................ 86

Table 157. X_OFS_USR register ................................................................ 86

Table 158. X_OFS_USR register description ........................................................ 86

Table 159. Y_OFS_USR register ................................................................ 86

LSM6DSO

List of tables

DS12140 - Rev 2

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