M95256-R datasheet(26/51 Pages) STMICROELECTRONICS

部件名	M95256-R

功能描述	256-Kbit serial SPI bus EEPROM with high-speed clock

PDF	51 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

26 / 51 page

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

•

Standby power mode

•

Deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be

started)

•

Not in the Hold condition

•

The Write enable latch (WEL) is reset to 0

•

Write in progress (WIP) is reset to 0

The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are

non-volatile bits).

7.2

Initial delivery state

The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The

Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.

M95256-W M95256-R M95256-DF

Power-up and delivery state

DS4712 - Rev 22

page 26/51

M95256-R 数据表(PDF) 26 Page - STMicroelectronics