HC05V7GRSSLASHD datasheet(122/170 Pages) NXP

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SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 108

MC68HC05V7 Specification Rev. 1.0

15.4

MDLC PROTOCOL HANDLER

The Protocol Handler is responsible for framing, collision detection, arbitration, CRC

generation/checking, and error detection. The Protocol Handler conforms to SAE J1850 -

Class B Data Communications Network Interface.

15.4.1

OUTLINE

The Protocol Handler contains three main blocks: the State Machine, Rx Shift Register and

Tx Shift Register, as shown below. Each block will now be described in more detail.

15.4.2

Rx & Tx SHIFT REGISTERS

The Rx Shift Register gathers received serial data bits from the J1850 bus and makes them

available in parallel form to the Rx Buffer. The Tx Shift Register takes data, in parallel form,

from the Tx Buffer and presents it serially to the State Machine so that it can be transmitted

onto the J1850 bus.

Physical Interface

To CPU

Protocol Handler

MUX Interface

CPU Interface

Rx/Tx

Buffers

To J1850 Bus

MDLC

Rx Shift Register

Figure 15-8:

MDLC Protocol Handler Outline

To CPU Interface & Rx/Tx Buffers

State Machine

To MUX Interface

Tx Shift Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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